(1) Field of the Invention
The present invention relates to a solid-state imaging device and a driving method thereof, and particularly to an amplifying solid-state imaging device and a driving method thereof.
(2) Description of the Related Art
In recent years, amplifying solid-state imaging devices using MOS imaging element have been attracting attention as a type of solid-state imaging device. The solid-state imaging device is of high sensitivity, and has an amplifier transistor which is set for each cell representing a pixel for amplifier signals detected by a photodiode. It has been requested, for the solid-state imaging device, to improve image quality by increasing the number of pixels (to megapixel).
With respect to such a solid-state imaging device, a solid-state imaging device with pixels aligned two-dimensionally, which can switch between selection and non-selection of pixels without a transfer selection switch has been proposed in Japanese Laid-Open Patent Application No. 2004-304771 (Patent Reference 1).
The solid-state imaging device according to the Patent Reference 1 shall be described hereafter. FIG. 1 is a diagram showing a circuit configuration of a conventional solid-state imaging device according to the Patent Reference 1.
This solid-state imaging device includes: an image area 504 in which each of plural unit cells 20 are placed two-dimensionally, and which has a photodiode 21, a readout transistor 22, a reset transistor 23, an amplifier transistor 24, and a floating diffusion unit (hereinafter referred to as FD unit) 25 directly connected to a gate of the amplifier transistor 24; a row selection circuit 510 for selecting the unit cells 20 per row; a first vertical signal line 509 which transmits signal voltage of unit cells 20 per column to a signal processing unit 511; the signal processing unit 511 which holds the signal voltage transmitted via the first vertical signal line 509 and cuts noise; a column selection circuit 512 for selecting the unit cells 20 per column; a horizontal signal line 513 for transmitting the signal voltage outputted from the signal processing unit 511 to an output amplifier 514; the output amplifier 514; and a group of load transistors 515.
FIG. 2 is a diagram showing a circuit configuration of the signal processing unit 511. In FIG. 2, two vertical signal lines connected to pixels of two columns are illustrated, corresponding to the image area 504 of the solid-state imaging device shown in FIG. 1.
The signal processing unit 511 includes: a sample-hold transistor 601 connected to the first vertical signal line 509; a clamp capacitance 602 connected to the first vertical signal line 509 via the sample-hold transistor 601; a second vertical signal line 603 connected to the first vertical signal line 509 via the clamp capacitance 602; a sampling transistor 604 connected to the second vertical signal line 603; a sampling capacitance 605 connected to the second vertical signal line 603 via the sampling transistor 604; a clamp transistor 606 connected to the clamp capacitance 602 and the sampling transistor 604; a column selection transistor 607 connected to the second vertical signal line 603; and a horizontal signal line capacitance 608 connected to the horizontal signal line 513.
The sample-hold transistor 601 is switched on in response to the application of a sampling pulse for raising the electric potential of an SP line to high level, and transmits signal voltage transmitted from the first vertical signal line 509 to the clamp capacitance 602.
The second vertical signal line 603 transmits signal voltage transmitted from the first vertical signal line 509 via the clamp capacitance 602.
The sampling transistor 604 is switched on in response to the application of a capacitance selection pulse for raising the electric potential of an SW line to high level, and transfers the signal voltage transmitted by the second vertical signal line 603, to the sampling capacitance 605.
The clamp transistor 606 is switched on in response to the application of clamp pulse for raising the electric potential of the CP line to high level, and reset the second vertical signal line 603, the clamp capacitance 602, and the sampling capacitance 605 to the electric potential of the CLDCNC line. The clamp capacitance 602 removes fixed pattern noise which varies from each unit cell 20 by holding the electric voltage between terminals A and B when the electric potential is reset.
The column selection transistor 607 is sequentially switched on in response to the application of a column selection pulse for raising the electric potential of a CSEL line to high level, and transfers the signal voltage accumulated in the sampling capacitance 605 to the horizontal signal line 513.
The sampling capacitance 605 holds the signal voltage which is read per row.
The operations of the abovementioned conventional solid-state imaging device are described hereafter with reference to a driving timing chart shown in (a) in FIG. 3.
When the unit cell 20 in mth row is selected, a row selection pulse for raising the electric potential of an LSET (m) line to high level is applied to the vertical selection transistor 26 in the unit cell 20 of mth row. The vertical selection transistor 26 is switched on. A source follower circuit is formed by the amplifier transistor 24 and a group of load transistors 515, and the voltage following the pixel power supply of the unit cell 20 is outputted from the source follower circuit to the first vertical signal line 509.
Next, a sampling pulse for raising the electric potential of the SP line to high level is applied to the sample-hold transistor 601. The sample-hold transistor 601 is switched on and the voltage outputted from the source follower circuit to the first vertical signal line 509 is held in the clamp capacitance 602. Here, a clamp pulse for raising the electric potential of the CP line to high level is applied to the clamp transistor 606. The clamp transistor 606 is switched on and the second vertical signal line 603 side of the clamp capacitance 602 is reset to the electric potential of the CLDCNC line. In addition, since a capacitance selection pulse for raising the electric potential of the SW line to high level is applied at the same time, the sampling transistor 604 is switched on, and the sampling capacitance 605 is reset to the electric potential of the CLDCNC line.
Next, a reset pulse (m) for raising the electric potential of the RESET (m) line to high level is applied to the reset transistor 23. The reset transistor 23 is switched on, and the electric potential of the FD unit 25 is reset. A gate voltage of the amplifier transistor 24 connected to the FD unit 25 is the voltage of the FD unit 25, and a voltage in accordance with this voltage, more specifically, an voltage given by (electric potential of the FD unit−Vt)×α is outputted to the first vertical signal line 509. Here, Vt is a threshold voltage of the amplifier transistor 24, and α is an voltage amplification rate.
Next, a clamp pulse for lowering the electric potential of the CP line to low level is applied to the clamp transistor 606. The clamp transistor 606 is switched off, and the electric potential of the second vertical signal line 603 falls in a floating state.
Next, a readout pulse (m) for raising the electric potential of READ (m) line to high level is applied to the readout transistor 22. The readout transistor 22 is switched on, and the signal charge which is accumulated in the photodiode 21 is transferred to the FD unit 25. The gate voltage of the amplifier transistor 24 connected to the FD unit 25 becomes the electric potential of the FD unit 25, and a voltage corresponding to this voltage, more specifically, a voltage calculated by (electric potential of the FD unit−Vt)×α is outputted to the first vertical signal line 509. Here, the clamp transistor 606 is switched off, since a clamp pulse for lowering the electric potential of the CP line to low high level is applied to the clamp transistor 606. In the sampling capacity 605, voltage change corresponding to a difference between the outputted voltage which is outputted to the first vertical signal line 509 when the electric potential of the FD unit 25 is reset and the voltage outputted to the first vertical signal line 509 when a signal charge accumulated in the photodiode 21 is transferred to the FD unit 25, is accumulated as a signal voltage of the unit cell 20 in mth row.
Next, a column selection pulse (m) for raising the electric potential of the CSEL (m) line to high level, a column selection pulse (m+1) for raising the electric potential of the CSEL (m+1) line to high level . . . is sequentially applied to the column selection transistor 607. Each of the column selection transistors 607 is sequentially switched on, and the signal voltage accumulated in the sampling capacitance 605 is sequentially outputted to the horizontal signal line 513.